The modeling of large-area semiconductor devices is complicated by the presence of distributed effects—i.e., parasitic capacitances, inductances, and resistances that are inherent in the device and interconnect structure. Such parasitics typically lead to non-uniform current flow and non-uniform behavior across the device, and can therefore significantly degrade the assumed scaling relationships while having a substantial impact on real-world performance of the design. In power metal-oxide semiconductor field effect transistors (MOSFETs), for example, the distributed parasitic resistances associated with the metal interconnects in large-area devices can reduce the achievable Rds(on)-area product of the MOSFET by 30% or more. Accordingly, it is desirable for parasitics to be accurately accounted for during simulation.
Since the contribution of parasitics to performance is strongly dependent on both the configuration of the device and the location of the external pin connections, accurate modeling preferably takes into account final device layout. One way of modeling and optimizing the performance of large area devices from the device layout is to represent the device as a three-dimensional distributed network of active and passive elements. These elements and their interconnection, which reflect the layout of the device, are distilled into a suitable “netlist.” However, generation of this netlist from the layout, in a standard analog design flow, is not straightforward. Furthermore, known methods of generating this netlist typically overestimate and/or underestimate the effects of various physical features.
Accordingly, there is a need for more efficient and accurate methods for simulating distributed effects in semiconductor device. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.